SummaryIn an environment of ExOS v6, where edge cache is working on web traffic, it can be seen that the overall bandwidth through the Exinda is decreased when going to version 7.4.0 or later of the firmware.
OverviewEdge cache is a way to cache highly visited web traffic and to be able to serve it back from the Exinda itself instead of requiring hosts requesting the same content to go out to the WAN and get a fresh copy. This traffic that is served back from the Exinda can traverse at LAN speeds and will prevent an often smaller external pipe from clogging up faster. Many people created an edge cach policy that could go beyond any such 'limits' that they put on it - such as 10% of the overall bandwidth for a general 'web' policy, ensuring that none of the non-edge cached traffic could go above 10%, but the edge cache traffic that did go out or come in was able to break that on v6 and early v7 firmware. After upgrading, it is possible to see a decrease in throughput for edge cached traffic that was previously seen going at speeds far exeeding even the license of the allowed bandwidth of the Exinda.
CauseOn ExOS v6 firmware, or in early versions of v7 (v7.0.0 - v7.0.3u1), running the edge cache engine ignores shaping on the inbound - that means that traffic being served from the Exinda completely ignored any circuit, virtual circuit or policy bandwidths on the bridge as it was going to the destination. This allowed for tremendous speeds on the LAN. However, this setting was changed in v7.4.0, as it was observed that this kind of behaviour could flood LAN traffic and overwhelm it, choking the pipe for other users. As of v7.4.0, traffic follows shaping rules at the circuit, virtual circuit and policies level.
This means that if the policy that the edge cache traffic belongs to is limited to a burst bandwidth of 10%, then even traffic being served from the edge cache will only use a maximum of 10% of the bandwidth on the LAN. A similar situation exists if the virtual circuit is limited in burst bandwidth, or there is a dedicated circuit for the edge cache and it is also limited in bandwidth.